Computer systems may comprise a plurality of parallel execution pipelines used to generate access addresses for load and store operations in the memory as well as data for storing in the memory. Where more than one pipeline is used to generate data values for storing in the memory instructions may pass through the pipelines at different rates so that data from the different pipelines may arrive at a memory access unit in an undesired order.
It is an object of the present invention to provide improved apparatus and methods for forming a queue of data in a desired order prior to a memory store operation.